glip  0.1.0-dev
The Generic Logic Interfacing Project


 Nexys4 DDR UART Loopback Demo
 VCU108 UART Loopback Demo

Detailed Description

The GLIP logic provides the interface between the UART controller and the user logic. This is essentially serialization and de-serialization of the UART data stream.

The Verilog toplevel module glip_uart_toplevel implements the common GLIP logic interface.

Additionally, the following signals are available in glip_uart_toplevel.

Port Name Width Direction Description
clk_io 1 IN I/O clock
uart_rx 1 IN RX signal
uart_tx 1 OUT TX signal
uart_cts_n 1 IN clear to send, flow control for TX. active low
uart_rts_n 1 OUT ready to send, flow control for RX. active low

The following parameters are available.

Name Description
FREQ_CLK_IO Frequency of the I/O clock clk_io
BAUD Baud rate (default: 115200)
WIDTH Width of the FIFO (fifo_*) ports. Supported values: 8 and 16. Default: 8
BUFFER_OUT_DEPTH Size of the output buffer (i.e. the buffer between the FPGA and the host) in bytes. Default: 4096 bytes